AND Gate | Gerbang AND | Basic Logical Gate | Gerbang Logika Dasar

AND Gate

The AND gate is a basic digital logic gate that implements logical conjunction (∧) from mathematical logic – AND gate behaves according to the truth table. 

A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1). 

If not all inputs to the AND gate are HIGH, LOW output results. 

The function can be extended to any number of inputs.

The AND gate with inputs A and B and output C implements the logical expression  C=A.B 

This expression also may be denoted as C = A∧B or C = A&B

In logic families like TTL, NMOS, PMOS and CMOS, and AND gate is built from a NAND gate followed by an inverter. 

In the CMOS implementation above, transistors T1-T4 realize the NAND gate and transistors T5 and T6 the inverter. 

The need for an inverter makes AND gates less efficient than NAND gates.

AND gates can also be made from discrete components and are readily available as integrated circuits in several different logic families.

Analytical representation

f(a,b) = a*b is the analytical representation of AND gate:

f(0,0) = 0*0 = 0 

f(0,1) = 0*1 = 0 

f(1,0) = 1*0 = 0 

f(1,1) = 1*1 = 1 

AND gates with multiple inputs are designated with the same symbol, with more lines leading in. 

While direct implementations with more than four inputs are possible in logic families like CMOS, these are inefficient. More efficient implementations use a cascade of NAND and NOR gates, as shown in the picture on the right below. 

This is more efficient than the cascade of AND gates shown on the right.

Gerbang AND

IC CMOS CD4081BE

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